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Hardware Reference Manual for i.MX53 Quick Start
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PORT_ID0 ?
Measured ? Voltage ?
PORT_ID1 ? Measured ? Voltage ?
MCIMX28LCD ?
MCIMXHDMICARD ?
18.0K ?
2.74K ?
1.61 ? V ?
0.54 ? V ?
130.0K ?
130.0K ?
2.32 ? V ?
2.32 ? V ?
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Table ? 3. ??
Port ? ID ? Resistor ? Values ?
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Over ‐ Voltage ? protection ? is ? sensed ? by ? the ? DCIN ? (B4) ? pin ? of ? the ? PMIC. ? The ? voltage ? sensed ? by ? this ? pin ? must ?
be ? between ? 4.5V ? and ? 5.5V. ? If ? the ? voltage ? meets ? this ? threshold ? value, ? the ? voltage ? seen ? at ? DCIN ? is ? blocked ?
from ? the ? DCIN_SEL ? (B3) ? pin ? and ? the ? P ‐ Channel ? MOSFET ? turns ? ON. ? Otherwise, ? DCIN_SEL ? remains ? high ?
and ? power ? is ? blocked ? from ? the ? rest ? of ? the ? Quick ? Start ? Board. ?
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The ? TP ? (L5) ? pin ? of ? the ? PMIC ? must ? be ? connected ? to ? ground. ? When ? designing ? with ? a ? 0.5mm ? pitch ? uBGA ?
package, ? there ? is ? limited ? space ? for ? vias ? and ? traces ? under ? the ? BGA. ? To ? assist ? with ? layout, ? Freescale ? has ?
confirmed ? that ? all ? pins ? labeled ? ‘NO ? CONNECT’ ? on ? the ? PMIC ? are ? in ? no ? manner ? bonded ? out ? to ? the ? silicon. ?
Therefore, ? for ? routing ? purposes, ? it ? is ? possible ? to ? route ? the ? trace ? from ? an ? interior ? pin ? through ? one ? or ?
more ? ‘NO ? CONNECT’ ? pins, ? or ? to ? place ? a ? via ? directly ? under ? a ? ‘NO ? CONNECT’ ? pin ? without ? requiring ? a ? via ‐ in ‐
pad ? technique. ? If ? the ? CAD ? Layout ? Engineer ? decides ? to ? place ? a ? via ? under ? a ? ‘NO ? CONNECT’ ? pin, ? the ? via ?
should ? not ? be ? tented ? as ? trapped ? gases ? during ? the ? assembly ? process ? may ? cause ? the ? solder ? ball ? from ? the ?
‘NO ? CONNECT’ ? pin ? to ? blow ? out ? into ? other ? pins ? and ? cause ? internal ? shorts ? under ? the ? BGA. ?
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The ? I2C ? communications ? channel ? between ? the ? Processor ? and ? the ? PMIC ? is ? Channel ? 1. ? This ? channel ? is ? only ?
shared ? with ? the ? accelerometer. ? This ? channel ? operates ? at ? TTL ? logic ? level ? of ? 1.8V. ? The ? NRESET ? (F10) ? pin ? of ?
the ? PMIC ? is ? directly ? connected ? to ? the ? Active ? Low ? POR_B ? (C19) ? pin ? of ? the ? i.MX ? Processor. ? The ? PMIC ? will ?
hold ? the ? Processor ? in ? the ? RESET ? state ? until ? all ? the ? power ? rails ? are ? fully ? powered. ? The ? NIRQ ? (E10) ? pin ? of ?
the ? PMIC ? is ? connected ? to ? the ? GPIO_ ? 16 ? (C6) ? pin ? of ? the ? Processor. ? This ? pin ? is ? not ? a ? dedicated ? pin ? for ? an ?
interrupt ? request, ? but ? can ? be ? programmed ? in ? Software ? to ? inform ? the ? Processor ? that ? the ? PMIC ? has ?
information ? to ? be ? given ? to ? the ? Processor. ?
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The ? PMIC ? has ? several ? different ? options ? for ? Pull ‐ Up ? levels ? on ? each ? of ? its ? output ? pins. ? In ? some ? cases, ?
VDDOUT ? is ? one ? option, ? along ? with ? power ? supplied ? to ? both ? the ? VDD_IO1 ? (L4) ? and ? VDD_IO2 ? (K4) ? pins ? as ?
Pull ‐ Up ? source. ? The ? exact ? source ? of ? Pull ‐ Up ? power ? is ? determined ? by ? the ? registry ? settings ? of ? the ? PMIC ? and ?
can ? be ? pre ‐ programmed ? at ? the ? factory ? as ? the ? designer ? wishes. ? Some ? Pull ‐ Up ? registry ? settings ? apply ? to ?
groups ? of ? pins, ? so ? care ? must ? be ? made ? in ? selecting ? which ? source ? power ? source ? is ? used ? for ? a ? particular ?
grouping ? of ? pins. ? The ? Dialog ? PMIC ? Datasheet ? contains ? much ? more ? detailed ? information ? on ? the ? registry ?
settings. ? For ? the ? Quick ? Start ? board, ? VLDO3 ? (3.3V) ? is ? connected ? to ? VDD_IO1 ? primarily ? to ? ensure ? that ? the ?
3V3_EN ? signal ? sent ? to ? the ? external ? regulator ? is ? sufficient ? to ? turn ? on ? the ? regulator, ? and ? VLDO8 ? (1.8V) ? is ?
connected ? to ? VDD_IO2 ? to ? provide ? for ? proper ? I2C ? TTL ? logic ? levels. ?
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Freescale Semiconductor
Hardware User Guide for i.MX53 Quick Start Board,
Preliminary Rev 0.91
37
PUBI – Public Use Business Information ?
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